Digital Electronics: Difference between latch and flip flop

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Difference between Latch and Flip Flop
#Difference #Latch #Flip #Flop

26 thoughts on “Difference between Latch and Flip Flop”
  1. I prefer a latch made with one input of a OR gate as the latch Set input. The OR gate output is connected to the input of a AND gate. The other input of the AND gate is connected to the output of an inverter. The inverter input is the Reset input of the Latch. The AND gate output is the Latch output and it is connected to the other input of the OR gate. My understanding is that some integrated circuit outputs can not be connected together without measures being taken to prevent damage. I call the latch circuit above a reset master since a high reset input always results in a low output. To avoid confusion figure any part of the circuit that has a high output is in some way connected to that gates or inverters power supply positive connection. To be honest I have not even tested the above circuit but have tested its relay logic equivalent (which is slightly different).

  2. Bro you have used nand gate and the put of the nand gate is y=a.b
    But you have taken the formula of nor gate🙄
    And you have told that we will consider memory when s=0 and r=0 but you have not done that please clarify my doubts

  3. I've learned a lot from Neso so thank you for your contributions. I hesitate to question you, but I feel compelled to point out after the difficulties I had in my class this week, that definitions of a flip-flop vary quite widely! For some people it's based on the type of synchronicity to a clock, for some people, it's just a gated latch, for some people its the existence of a clock, for others it's the one cycle time delay created by the M/S setup- which serves to prevent glitches and nothing else! Wikipedia uses the terms interchangeably! All the sources contradict each other and, to a new student, it's horribly and needlessly confusing! You could be the ultimate source by explaining this situation and elaborating on why your interpretation is the most credible.

  4. Won't the flip flop as enabled by the clock at 5:05 be functional only when the clock is high? Like I don't get why is it edge-triggered/edge-sensitive in this particular design. Even with a clock, the circuit should remain functional only when the level is high, and not just during transition. Am I right?

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