Wednesday, May 25, 2022

# Counters (Part 5b) – VHDL Structural Architecture vs. Behavioural Architecture

Um hello and welcome to this rather short video so what i want to do in this video is just basically make this somewhat a continuation of my last video and all i'm thinking of doing here is let's actually define this counter exactly like it was in counter one in other words let's go ahead and include set n .

In standard logic and clear n also an input standard logic okay so let's define both in here and then um we now need to specify what happens to .

Them in our process so if sets n um okay we started with clear n if claire n is equal to zero then um we our s underscore q .

We assign is zero to that so this is the integer code so let's we'll use zero there we just specified that zero else if um set n is equal to zero .

Then uh s underscore s underscore q we are assigned one to its for the set state now else in the else case now we now have this um piece of code in here it goes into the else case so i need to bring another end if .

So i think this should be about it um our test bench does not test for um does that test for set n or clair n it's always a good idea to test for certain and clear n so to test for any inputs that you put in there because if you don't test for a particular input you you may not be able to tell whether or not the .

Code you put in the code is actually working like it showed so i'll supply a signal to um well let's make it set n um 20 is a round figure let me get clear and 10 okay declare and no let's just set yeah click end as i assign a value to clear n an active an active transition active value to .

Clear n i'll copy this two lines of code to hopefully save me some time next analysis to set it then i want to do the same thing for set n set n and then i'll after that just put this loop again just so that it's .

We have something to check okay so this is about it this is our test page test been definitely defined next thing i want to do is go ahead and compile this once again um i'll end the previous simulation i had running then i'll go ahead and compile okay sorry i've pasted something in here again .

Um cancer cancer gas gas gas against cancer castle compile um get compiled synchronous counter compile synchronous counter compiles with no error oh sorry let's compile the test bench compile the test bench uh okay it has a bunch of errors .

Why oh yes so sorry about that i need to go back and check my vs code okay so vs code firstly i will take this out because we no longer need it in there um actually don't need it anymore since i'm using this definition over here then i've not done any port mapping to .

My um set n and my clear end so i need to create signals for those two sig now signal um s underscore set n and s underscore clear n and type standard logic and initialize them to one okay so that is about it i think we okay .

Now so now i need to do a pot mapping for those two um set n map to s underscore sets n and we have a put a comma over here so we don't end up with an error play n .

Will get mapped to s underscore player n so we have this set out and then next thing we need to do is i need to compile this and when i'm done compiling this i can run this simulation so let's go ahead and compile this this time we should have no error nope eight errors in there um let's see .

Illegal sorry loading entity this year line 24 let's see what's on line 24 line 24 is complaining about this oh sorry so sorry about this this should be s underscore because um we're not writing we're actually writing to the signal not to the particular parts .

Yes so this should be fine now and run the compilation once again okay good so no errors this time let's go ahead and run this simulation i said this will be a short video my apologies has run a little longer than i thought it would run okay so add waves um just to run the simulation make sure .

That all is well then where i'm actually going to is i want to check this out in quarters it runs 500 nanoseconds no errors down there just check full this is fine pop it out and see what this looks like again let's look at this in full so we see where our classic now comes in where our set signal comes in .

Um okay so our claire now this did not do anything so our set in our play actually did not um operate on our code so we need to check that again something happened in our counter when we when the set signal came active um nothing happened to our sq when the .

Um classic now also came up active nothing happened to our sq so this is not doing what we expected to do over here the else is working that is working fine okay yes the reason is this our sensitivity list does not contain uh clear n and our .

Set end so unless it just happens that those signals change at the same time the clock changes this process will never fire just for them so let's go back to model sim um now i could have just written the finished code and compiled it and shown it to you but i always prefer to write the code here while you're .

Watching so that you can learn from whatever mistakes it is i make so compile i need to compile both of them this time um sync contact compiles test bench compiles run the simulation and and again that's a good reason to always simulate and not just assume that yeah okay compile that that message is .

Perfectly fine and we run the compilation and then we saw that apparently actually we ran the simulation and we saw that apparently there were errors in it um okay i've not run it yet 100 nanoseconds run seems to run without errors now when we clear it clears where we .

Tell it to set it does not set so it's cleared here and instead of setting what happened it just went up one bit so why is that okay so another thing to check .

In our code so let's get back here when sq was set to zero yes and here oh i said sq set to one now remember if if we're working with okay so we should set this to seven not to one because this is an integer okay if it were a um a vector or a single bt yes we could make it one but .

In this case it's a vector so it actually works exactly like we told it to be but let's set it to seven so that we have all ones like we had in the last code remember what i'm doing here is i'm just trying to make make this exactly be like the counter we designed and um one so compare apples to apples we look at the number of resources that were used .

In both cases compiled as bench as well and now i'll go ahead and simulate this run the simulation add to wave okay bring the wave back to the front it keeps on hiding the wave bring the wave back to the front run this for 100 nanoseconds run .

Full and yes so now it sets to one one one and then the next active clock transition takes it back to zero and it runs through the sequence like we expected to run so it runs for 20 nanoseconds or it has 20 loops of the iteration and then it clears and then it sets everything and then runs through the entire thing once .

Again so now let's get to quartus and we want to view this is counter sync counter one this encounter two i have done some modifications so let's um compile this once again has rod successfully do you want to run it again yes i want to run it again since we have modified the code yes reload okay so just wanna make sure .

It has seen the modified code so we want this to run once this is complete then we'll take a look at two things we'll take a look at the netlist viewer but particularly we're interested in the compilation report to see the number of elements so now it uses more elements notice nine logic elements but still three registers and six pins .

Um i'm not quite sure why it's using six pins uh that's fewer pins that we had in the um sink out of one i could check that later i don't want to check that with our time now we can take a look at the design and see what it's like now it includes a play and it includes a um set so you .

Have your preset are your play that are included and you have logic included for that again i'll not try to analyze this now but take note it makes use of nine logic elements whereas sync counter one makes use of 12 logic elements so that um explains oh okay the reason is the reason for the number of pins is .

Um i use two down to zero and that down to zero um yeah apples to apples oranges or oranges so sorry about that i will go ahead and make everything exactly the same so that we see whether we use fewer number of logic elements to see if my claim is correct nine changes from zero to um .

Zero zero and this also from zero to zero zero okay now i need to compile this once again this time i'll just compile this in quartus because this is encounter one and sync counter two reload this yes reload thank you compile .

To just compare and see total number of logic elements that i used particularly i want to see are we using fewer resources are using more resources are we better off doing a structural design than we are just simply allowing it to try to figure things out on its own um .

If you're good at design ideally what should happen is that your own design should be better than whatever it comes up with but okay so total number of logic elements 10. and for sting counter one we had 12 okay if i just show that for sink counter one we had 12 logic elements but for synchrons you have 10 logic elements so .

Comparatively it seems like we're using fewer resources when we write the code um like we did in this case now also be in mind that this makes use of the integer you could ask the question you could actually try this on your on your own time run it with the unsigned okay run the code with unsigned instead .

Of with um with integer and just see how many um yeah i sometimes can be a little stubborn and i'll go ahead and run it here since it shouldn't take too much time i'll just need to comment out some lines of code and that shouldn't take too long to comment out .

So i'll comment out these lines of code okay i'll just do it one by one there's a command for commenting out in block but i don't take time to figure that out okay so i think we're about done let's go back to quartus and this is yes think counter to reload and analyze synthesize let's compile this and see how this runs .

Hopefully i i did everything and i haven't introduced any error into this i think i complemented out everything i showed this is taking it longer than i i expected so let's just take a look at one last time yeah i think it's fine uh okay sorry about this so um i really want to keep this video .

Um short so that on site types don't match intra integer literal yes um that is here the fact that i have changed things so now i have to make this zero zero zero and make this one one one okay anything else no i think that .

Should be about fine so this time it should run through um everything crossed okay it should run through this time and i think we should be fine and i should be able to end this video at this point again i apologize this has gone on longer than i thought it would i thought it would just be a two to three .

Minutes well a five minute video in in the most and okay it seems like we should be out of the weeds now yes so it has run through and again ten logic elements three registers not much difference um in the um in the number of elements that i used .

Whether i use unsigned or whether you made use of integer this also not so different from what you had um somewhat different but not too different from what you had so that's it for this video i just wanted this to be an addendum and addition to the last video that we had thank you

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